學術表現：

1. N. D. Chien, N. V. Hao, L. V. Tung, and C. H. Shih, "Semiconductor-Thickness-Dependent Design of Hetero-Gate Dielectric in Double-Gate TFETs," in 2020 IEEE Eighth International Conference on Communications and Electronics (ICCE), 13-15 Jan. 2021, pp. 230-234
2. J. J. Tsai, W. F. Wu, Y. H. Chen, H. J. Teng, N. D. Chien, and C. H. Shih, "Effects of High Temperatures on Cell Reading, Programming, and Erasing of Schottky Barrier Charge-Trapping Memories," IEEE Transactions on Device and Materials Reliability, vol. 19, no. 2, pp. 426-432, 2019
3. H. J. Teng, Y. H. Chen, N. D. Chien, and C. H. Shih, "Negative Capacitance in Short-Channel Tunnel Field-Effect Transistors," in 2019 Silicon Nanoelectronics Workshop (SNW), 9-10 June 2019, pp. 1-2
4. Y. H. Chen, C. H. Shih, H. J. Teng, and C. Lien, "Metallic Source/Drain Ge-Based Charge-Trapping Memory Cells," in 2019 Silicon Nanoelectronics Workshop (SNW), 9-10 June 2019, pp. 1-2
5. C. H. Shih, T. S. Kang, Y. H. Chen, H. J. Teng, and N. D. Chien, "Dopant-segregated metal source tunnel field-effect transistors with schottky barrier and band-to-band tunneling," in 2017 Silicon Nanoelectronics Workshop (SNW), 4-5 June 2017, pp. 53-54
6. N. D. Chien, N. T. Thu, C. H. Shih, and L. T. Vinh, "Different scalabilities of N- and P-type tunnel field-effect transistors with Si/SiGe heterojunctions," in 2016 International Conference on IC Design and Technology (ICICDT), 27-29 June 2016, pp. 1-4
7. N. D. Chien, C. H. Shih, Y. H. Chen, and N. T. Thu, "Increasing drain voltage of low-bandgap tunnel field-effect transistors by drain engineering," in 2016 International Conference on Electronics, Information, and Communications (ICEIC), 27-30 Jan. 2016, pp. 1-4
8. Y. H. Chen, J. J. Tsai, Y. X. Luo, and C. H. Shih, "Iterative programming analysis of dopant-segregated multibit/cell Schottky barrier charge-trapping memories," in 2015 15th Non-Volatile Memory Technology Symposium (NVMTS), 12-14 Oct. 2015, pp. 1-3
9. Y. H. Chen, Y. X. Luo, J. J. Tsai, and C. H. Shih, "Drain-controlled ambipolar conduction and hot-hole injection in Schottky barrier charge-trapping memory cells," in 2015 15th International Workshop on Junction Technology (IWJT), 11-12 June 2015, pp. 81-82
10. Y. H. Chen, N. D. Chien, J. J. Tsai, Y. X. Luo, and C. H. Shih, "Short-drain effect of 5 nm tunnel field-effect transistors," in 2015 Silicon Nanoelectronics Workshop (SNW), 14-15 June 2015, pp. 1-2
11. Chun-Hsing Shih* and Nguyen Van Kien, “Sub-10-nm asymmetric junctionless tunnel field-effect transistors,” IEEE Journal of the Electron Devices Society, Vol. 2, pp. 128-132, Sep. 2014. (SCI/JCR2015, IF: 1.543, Rank: 107/257 in Electrical/Electronic Engineering)
12. Chun-Hsing Shih* and Nguyen Dang Chien, “Design and modeling of line-tunneling field-effect transistors using low-bandgap semiconductors,” IEEE Transactions on Electron Devices, Vol. 61, pp. 1907-1913, June 2014. (SCI/JCR2012, IF: 2.062, Rank: 44/242 in Electrical/Electronic Engineering)
13. Chun-Hsing Shih* and Yan-Xiang Luo, “Effects of dopant-segregated profiles on Schottky barrier charge-trapping Flash memories,”  IEEE Transactions on Electron Devices,  Vol. 61, pp. 1361-1368, May, 2014. (SCI/JCR2012, IF: 2.062, Rank: 44/242 in Electrical/Electronic Engineering)
14. Chun-Hsing Shih* and Nguyen Dang Chien, “Physical properties and analytical models of band-to-band tunneling in low-bandgap semiconductors,” Journal of Applied Physics, Vol. 115, 044501(8pp), Jan. 2014. (SCI/JCR2012, IF: 2.210, Rank: 31/127 in Applied Physics)
15. Chun-Hsing Shih* and Jui-Kai Hsia, “Operation and scalability of dopant segregated Schottky barrier MOSFETs with recessed channels,” Semiconductor Science and Technology, Vol. 28, 115008(10pp), Nov. 2013. (SCI/JCR2012, IF: 1.921, Rank: 51/242 in Electrical/Electronic Engineering)
16. We Chang, Chun-Hsing Shih*, Yan-Xiang Luo, Jui-Kai Hsia, Wen-Fa Wu, and Chenhsin Lien, “Localized two-bit/cell Schottky barrier nanowire SONOS memory using source-side electron programming,” IEEE Transactions on Nanotechnology, Vol. 12, pp. 760-765, Sep. 2013. (SCI/JCR2012, IF: 1.800, Rank: 63/242 in Electrical/Electronic Engineering).
17. Chun-Hsing Shih* and Nguyen Dang Chien, “Physical operation and device design of short-channel tunnel field-effect transistors with graded silicon-germanium heterojunctions,” Journal of Applied Physics, Vol. 113, 134507(7pp), Apr. 2013. (SCI/JCR2012, IF: 2.210, Rank: 31/127 in Applied Physics)
18. Chun-Hsing Shih*, Jhong-Sheng Wang, Nguyen Dang Chien, and Ruei-Kai Shia, “On-current limitation of high-k gate insulator MOSFETs,” Solid-State Electronics, Vol. 78, pp. 87-91, Dec. 2012. (SCI/JCR2012, IF: 1.482, Rank: 88/242 in Electrical/Electronic Engineering)
19. Chun-Hsing Shih*, We Chang, Wen-Fa Wu, and Chenhsin Lien, “Multi-level Schottky barrier nanowire SONOS memory with ambipolar N- and P-channel cells,” IEEE Transactions on Electron Devices, Vol. 59, pp. 1614-1620, June 2012. (SCI/JCR2012, IF: 2.062, Rank: 44/242 in Electrical/Electronic Engineering)
20. Chun-Hsing Shih*, Ji-Ting Liang, and Yan-Xiang Luo, “Reading operation and cell scalability of nonvolatile Schottky barrier multibit charge-trapping memory cells,” IEEE Transactions on Electron Devices, Vol. 59, pp. 1599-1606, June 2012. (SCI/JCR2012, IF: 2.062, Rank: 44/242 in Electrical/Electronic Engineering)
21. Chun-Hsing Shih* and Nguyen Dang Chien, “Sub-10nm tunnel field-effect transistor with graded Si/Ge heterojunction,” IEEE Electron Device Letters, Vol. 32, pp. 1498-1500, Nov. 2011.  (SCI/JCR2012, IF: 2.789, Rank: 26/242 in Electrical/Electronic Engineering)
22. Chun-Hsing Shih*, Wei Chang, Yan-Xiang Luo, Ji-Ting Liang, Ming-Kun Huang, Nguyen Dang Chien, Ruei-Kai Shia, Jr-Jie Tsai, Wen-Fa Wu, and Chenhsin Lien, “Schottky barrier silicon nanowire SONOS memory with ultralow programming and erasing voltages,” IEEE Electron Device Letters, Vol. 32, pp. 1477-1479, Nov. 2011.  (SCI/JCR2012, IF: 2.789, Rank: 26/242 in Electrical/Electronic Engineering)
23. Chun-Hsing Shih*, Ji-Ting Liang, Jhong-Sheng Wang, and Nguyen Dang Chien, “A source-side injection lucky electron model for Schottky barrier metal-oxide-semiconductor devices,” IEEE Electron Device Letters, Vol. 32, pp. 1331-1333, Oct. 2011. (SCI/JCR2012, IF: 2.789, Rank: 26/242 in Electrical/Electronic Engineering)
24. Ji-Ting Liang, Chun-Hsing Shih*, Wei Chang, Yan-Xiang Luo, Ming-Kun Huang, Nguyen Dang Chien, Wen-Fa Wu, Sau-Mou Wu, Chenhsin Lien, Riichiro Shirota, Chiu-Tsung Huang, Su Lu, and Alex Wang, “Impact of edge encroachment on programming and erasing gate current in NAND-type Flash memory,” IEEE Transactions on Electron Devices, Vol. 58, pp. 1257-1263, Apr. 2011. (SCI/JCR2012, IF: 2.062, Rank: 44/242 in Electrical/Electronic Engineering)
25. Chun-Hsing Shih*, Yan-Xiang Luo, and Sheng-Pin Yeh, “Design considerations of nanoscale Schottky barrier Flash memory with source-side injection programming,” Japanese Journal of Applied Physics, Vol. 50, 024202(7pp), Feb. 2011. (SCI/JCR2012, IF: 1.067, Rank: 81/127 in Applied Physics)
26. Chun-Hsing Shih* and Ji-Ting Liang, “Nonvolatile Schottky barrier multibit cell with source-side injected programming and reverse drain-side hole erasing,” IEEE Transactions on Electron Devices, Vol. 57, pp. 1774-1780, Aug. 2010. (SCI/JCR2012, IF: 2.062, Rank: 44/242 in Electrical/Electronic Engineering)
27. Chun-Hsing Shih* and Ching-Chang Lin, “Dopant segregated Schottky barrier MOSFETs with an insulated dielectric oxide,” Semiconductor Science and Technology, Vol. 25, 065003(6pp), June 2010. (SCI/JCR2012, IF: 1.921, Rank: 51/242 in Electrical/Electronic Engineering)
28. Chun-Hsing Shih* and Jhong-Sheng Wang, “Analytical drift-current threshold voltage model of long-channel double-gate MOSFETs,” Semiconductor Science and Technology, Vol. 24, 105012(8pp), Oct. 2009. (SCI/JCR2012, IF: 1.921, Rank: 51/242 in Electrical/Electronic Engineering)
29. Chun-Hsing Shih* and Jhong-Sheng Wang, “Threshold voltage of ultrathin gate-insulator MOSFETs,” IEEE Electron Device Letters, Vol. 30, pp. 278-281, Mar. 2009. (SCI/JCR2012, IF: 2.789, Rank: 26/242 in Electrical/Electronic Engineering)
30. Chun-Hsing Shih*, Sheng-Pin Yeh, Ji-Ting Liang, and Yan-Xiang Luo, “Source-side injection Schottky barrier Flash memory cells,” Semiconductor Science and Technology, Vol. 24, 025013(5pp), Feb. 2009. (SCI/JCR2012, IF: 1.921, Rank: 51/242 in Electrical/Electronic Engineering)
31. Sheng-Pin Yeh, Chun-Hsing Shih*, Jeng Gong, and Chenhsin Lien, “Latent noise in Schottky barrier MOSFETs,” Journal of Statistical Mechanics: Theory and Experiment, P01036(12pp), Jan. 2009 (focus issue). (SCI/JCR2012, IF: 1.866, Rank: 29/132 in Mechanics, 11/55 in Mathematical Physics)
32. Chun-Hsing Shih* and Sheng-Pin Yeh, “Device considerations and design optimizations of dopant segregated Schottky barrier MOSFETs,” Semiconductor Science and Technology, Vol. 23, 125033(10pp), Dec. 2008. (SCI/JCR2012, IF: 1.921, Rank: 51/242 in Electrical/Electronic Engineering)
33. Ching-Yuan Ho and Chun-Hsing Shih*, “Edge encroachments and suppressions of tunnel oxide in Flash memory cells,” IEEE Electron Device Letters, Vol. 29, pp. 1159-1162, Oct. 2008. (SCI/JCR2012, IF: 2.789, Rank: 26/242 in Electrical/Electronic Engineering)
34. Chun-Hsing Shih* and Sheng-Pin Yeh, “A dual workfunction gate for thin-gate-insulator Schottky barrier MOSFETs,” IEEE Transactions on Electron Devices, Vol. 55, pp. 2521-2525, Sep. 2008. (SCI/JCR2012, IF: 2.062, Rank: 44/242 in Electrical/Electronic Engineering)
35. J.-S. Wang, W. P.-N. Chen, Chun-Hsing Shih*, C. Lien, P. Su, Y.-M. Sheu, D. Y.-S. Chao, and K. Goto, “Mobility modeling and its extraction technique for manufacturing strained-Si MOSFETs,” IEEE Electron Device Letters, Vol. 28, pp. 1040-1043, Nov. 2007. (SCI/JCR2012, IF: 2.789, Rank: 26/242 in Electrical/Electronic Engineering)
36. Chun-Hsing Shih* and Chenhsin Lien, “Dependences of short-channel effect on doping profiles for nanoscale metal-oxide-semiconductor field-effect transistor,” Japanese Journal of Applied Physics, Vol. 45, pp. 3959-3971, May 2006. (SCI/JCR2012, IF: 1.067, Rank: 81/127 in Applied Physics)
37. Chun-Hsing Shih*, Yi-Min Chen, and Chenhsin Lien, “An analytical threshold-voltage roll-off equation for MOSFET using effective-doping model,” Solid-State Electronics, Vol. 49, pp. 808-812, May 2005. (SCI/JCR2012, IF: 1.482, Rank: 88/242 in Electrical/Electronic Engineering)
38. Chun-Hsing Shih*, Yi-Min Chen, and Chenhsin Lien, “An analytical model of short-channel effect for MOSFET with insulated shallow extension,” Japanese Journal of Applied Physics, Vol. 43, pp. 7993-7996, Dec. 2004. (SCI/JCR2012, IF: 1.067, Rank: 81/127 in Applied Physics)
39. Chun-Hsing Shih, Yi-Min Chen, and Chenhsin Lien*, “Design strategy of localized halo profile for achieving sub-50 nm bulk MOSFET,” Microelectronics Reliability, Vol. 44, pp. 1069-1075, July 2004. (SCI/JCR2012, IF: 1.137, Rank: 119/242 in Electrical/Electronic Engineering)
40. Chun-Hsing Shih, Yi-Min Chen, and Chenhsin Lien*, “An insulated shallow extension structure for bulk MOSFET,” IEEE Transactions on Electron Devices, Vol. 50, pp. 2294-2297, Nov. 2003. (SCI/JCR2012, IF: 2.062, Rank: 44/242 in Electrical/Electronic Engineering)